Dual-port negative level sensitive reset data retention latch

ABSTRACT

In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D 2,  the clock signals CKT and CLKZ, the retain control signal RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D 2  is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

This application claims priority from Provisional Application No. 61/870,086, filed Aug. 26, 2013.

BACKGROUND

Several trends presently exist in the semiconductor and electronics industry. Devices are continually being made smaller, faster and requiring less power. One reason for these trends is that more personal devices are being fabricated that are relatively small and portable, thereby relying on a battery as their primary supply. For example, cellular phones, personal computing devices, and personal sound systems are devices that are in great demand in the consumer market. It is also important that data on these devices be retained even when no power is supplied to the electronic device. Non-volatile memory circuits and non-volatile logic circuits are often used to meet these requirements.

Non-volatile logic implementation often requires updating sequential elements, such as latches, from a source external to the sequential element, such as a non-volatile memory. When non-volatile logic circuits are implemented to allow the updating of sequential elements, it is desired that the implementation of the non-volatile logic circuit does not significantly slow the operation of a sequential element.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a dual-port negative level sensitive reset data retention latch according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a clocked inverter according to an embodiment of the invention.

FIG. 3 is a schematic diagram of a dual-port latch according to an embodiment of the invention.

FIG. 4 is a schematic diagram of a tri-state inverter. (Prior Art)

FIG. 5 is a schematic diagram of a clocked inverter according to an embodiment of the invention.

FIG. 6 is a schematic diagram of a tri-state inverter. (Prior Art)

FIG. 7 is a timing diagram showing signals SS, RET, REN, D1, CKT, SX, QN and the output of the latch Q according to an embodiment of the invention.

FIG. 8 is a timing diagram showing signals RET, CKT, REN, D2, SS, SX, QN, and Q according to an embodiment of the invention.

FIG. 9 is a timing diagram showing signals RET, REN, D2, SS, SX, QN, and Q according to an embodiment of the invention.

DETAILED DESCRIPTION

In an embodiment of the invention a dual-port negative level sensitive reset data retention latch 100 contains a clocked inverter 102, an inverter 110, a dual-port latch 108 and a logic circuit 112 used to create internal clock CLKZ from clock CKT. The clocked inverter 102 is configured to receive a first data bit D1, a retain control signal RET, a reset control signal REN and clock signals CLKZ and CKT. The dual-port latch 108 is configured to receive the output QN from the clocked inverter 102, data input D2, clock signals CLKZ and CKT, a retain control signal RET, the reset control signal REN and control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output QN of the clocked inverter 102 or the second data bit D2 is latched in the dual-port latch 108.

Non-volatile logic implementations often require updating sequential elements (e.g. latches and flip flops) from an external source (e.g. non-volatile memory). In an embodiment of the invention, the dual-port latch includes 108 a second data input (port) D2. The second data input D2 is used to insert data from an external source. A tri-state inverter is added to the dual-port latch 108 to accommodate the second data input. This will be explained in more detail later in the specification. When external data needs to be inserted into the dual-port latch, the tri-state inverter is enabled.

The circuitry used to add the second input (D2) to the dual-port latch 108 is not part of the critical timing path of the dual-port negative level sensitive reset data retention latch 100. As a result, change to the regular performance of the dual-port negative level sensitive reset data retention latch 100 is negligible.

FIG. 1 is a block diagram of a dual-port negative level sensitive reset data retention latch 100 according to an embodiment of the invention. In a functional (i.e. normal) mode of operation, the retention mode signal RET is held at a logical low level, the reset control signal REN is held at a logical high level, the control signal SS is held at a logical low level and the binary compliment signal SSN of the control signal SS is held at a logical high level. Power is needed for functional mode operation so power supply VDD1 and power supply VDD2 are applied to the dual-port negative level sensitive reset data retention latch 100.

FIG. 7 is a timing diagram showing reset signal REN, retention signal RET, control signal SS, data bit D1, clock signals CKT and CLKZ and the output Q of the dual-port negative level sensitive reset data retention latch 100 during the functional mode of operation. Because the RET is held at a logical low level and REN is held at a logical high value, the binary logical compliment of D1 is passed to the output QN when clock signal CKT transitions from a high to low logical value. FIG. 2 illustrates an embodiment of a clocked inverter 102. QN is then presented to an input of the dual-port latch 108 and the inverter 110. The output of inverter 110 drives the signal Q.

FIG. 3 is a schematic diagram of a dual-port latch 108 according to an embodiment of the invention. The dual-port latch 108 includes a first tri-state inverter 302 (see FIG. 4 for an embodiment of the first tri-state inverter 302) with tri-state controls SS and SSN, a clocked inverter 304 (see FIG. 5 for an embodiment of the clocked inverter 304) with controls RET and REN and a second tri-state inverter 306 (see FIG. 6 for an embodiment of the second tri-state inverter 306) with tri-state controls SS and SSN.

When the dual-port negative level sensitive reset data retention latch 100 is operating in the functional mode and the clock signal CKT is at a low logic level (logic one), the tri-state inverter 302 is active and drives node SX of the dual-port latch 108 to the complimentary logical value of QN. When the clock signal CKT transitions from a low logical level to a high logical level, the logical level on the QN is latched by the clocked inverter 304. In this embodiment of the invention, an inverter 110 is used to buffer QN. However, non-inverting buffers may be used as well. The tri-state inverter 306 is tri-stated in this mode because SS is a logical low level and SSN is a logical high level. As a result, D2 is not transferred to node SX.

However, during another functional mode of operation, data D2 may be written directly to the dual-port latch 108 (See FIG. 8). During this functional mode, the clock signal CKT is held at a high logical level, CLKZ is held at a low logical level, control signal REN is held at a logical high level, control signal RET is held inactive (i.e. logic zero) with control signal SS held at a logical high level and control signal SSN held at logical low level.

When control signal SS is held at a logical high level and control signal SSN is held at logical low level, tri-state inverter 306 is able to drive the complimentary value of D2 onto node SX of the dual-port latch 108. Because CLKZ and RET are held at logical low levels and CKT and REN are held at logical high levels, the clocked inverter 304 is active and drives node QN to the logical value of D2. The inverter 110 then inverts the logical value on node QN to its compliment. In this example, the compliment of D2 is presented on node Q. Data signal D2 must be held for the period t3 to insure that the correct value of D2 is latched. Also, control signal SS must remain at logical high value for time t2 to insure that the correct value D2 is latched.

When control signal SS is driven from a logical high level to a logical low level and SSN is driven from a logical low level to a logical high level, the tri-state inverter 306 is tri-stated and tri-state inverter 302 becomes active latching the logical value on node QN of the dual-port latch 108.

The dual-port negative level sensitive reset data retention latch 100 can also be operated to retain data (RET mode) in the dual-port latch 108 (power supply VDD2 is active) when clocked inverter 102 and inverter 110 are powered off (i.e. power supply VDD1 is inactivated). Because the dual-port negative level sensitive reset data retention latch 100 is being operated in the RET mode, the retention mode signal RET is held at a logical high level, and the SS and SSN signals are at a logic 0 and a logic 1 respectively. Because power is not supplied to clocked inverter 102, QN is not actively driven by clocked inverter 102. In this manner, the data being retained in the dual-port latch 108 will not be inadvertently corrupted by the indeterminate output value of the clocked inverter 102 (the input is indeterminate as the supply VDD1 is inactive or floating). All other inputs are don't-cares.

During retention mode of operation, data D2 may be written directly to the dual-port latch 108. During this retention mode, the control signal SS is driven to a logical high level following RET being driven to a logical high value (see FIG. 9). The clock signals CKT and CLKZ are don't cares in this mode of operation in this embodiment. Before time t1, D2 does not have to be driven to a logical level (i.e. D2 may be a logical one, a logical zero, floating or tri-stated). D2 must be driven to a logical one or a logical zero some time t1 before the control signal SS transitions from a logical zero to a logical one. D2 must be stable for time t4 before the control signal SS transitions from a logical one to a logical zero and remain stable for time t3 afterwards in order to ensure D2 will be correctly latched.

Because the control signal SS is driven to a logical high level following RET being driven to a logical high value, the tri-state inverter 302 is tri-stated and does not drive node SX of the dual-port latch 108. Because the control signal SS is driven to a logical high and control signal SSN is driven to a logical low value, the tri-state inverter 306 is active and drives node SX to the complimentary value presented on D2. Because RET is a logical high value, the clocked inverter 304 is active and drives node QN. When the control signal SS returns to a logic low level and SSN returns to a logic high level, the value stored on node QN is latched between tri-state inverter 302 and clocked inverter 304 while tri-state inverter 306 is tri-stated. Data signal D2 must be held for the period t3 to insure that the correct value of D2 is latched. Also, control signal SS must remain at logical high value for time (t2+t4) to insure that the correct value D2 is latched. Under this condition, the data written from D2 remains latched in the dual-port latch 108 during retention mode.

When an embodiment of the invention is asynchronously reset (i.e. the active reset signal REN can be issued at any time irrespective of the logical value of the clock signals CKT and CLKZ) during functional mode (i.e. RET remains a logical zero), the dual-port latch 108 shown in FIG. 1 may be reset to a logical one on its output QN by driving REN to a logical zero. The clocked inverter 102 will not “fight” QN being driven to a logical high value because the pull-down leg to ground of clocked inverter 102 is open. The pull-down leg to ground is open because the signal REN is low.

The foregoing description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiments were chosen and described in order to best explain the applicable principles and their practical application to thereby enable others skilled in the art to best utilize various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments except insofar as limited by the prior art. 

What is claimed is:
 1. A dual-port negative level sensitive reset data retention latch comprising: a clocked inverter configured to receive a first data bit (D1), clock signal (CKT), clock signal (CLKZ), a reset control signal (REN) and retention mode control (RET) wherein (CKT), (CLKZ), (RET) and (REN) determine whether the data output (QN) from the clocked inverter is the binary compliment of data bit (D1) or an indeterminate value; a dual-port latch configured to receive the output (QN) of the clocked inverter, a second data bit (D2), the clock signal (CKT), the clock signal (CLKZ), the retain control signal (RET), a reset control signal (REN), a latch control signal (SS) and a latch control signal (SSN) wherein signals (CKT), (CLKZ), (RET), (REN), (SS) and (SSN) determine whether the output (QN) of the clocked inverter or the second data bit (D2) is latched in the dual-port latch.
 2. The dual-port negative level sensitive reset data retention latch of claim 1, further comprising a first inverter wherein the first inverter receives the output (QN) and the first inverter outputs (Q).
 3. The dual-port negative level sensitive reset data retention latch of claim 1, further comprising a buffer wherein the buffer receives the output (QN) and the buffer outputs the same logical value of (QN).
 4. The dual-port negative level sensitive reset data retention latch of claim 2 wherein the clocked inverter and the first inverter receive power from a first power supply (VDD1); wherein the dual-port latch receives power form a second power supply (VDD2).
 5. The dual-port negative level sensitive reset data retention latch of claim 4 wherein the first power supply (VDD1) is turned off and the second power supply (VDD2) is turned on during operation of a retention mode; wherein power is only supplied to the dual-port latch.
 6. The dual-port negative level sensitive reset data retention latch of claim 1 wherein control signals (SS), (SSN), (REN) and (RET) are controlled external to the dual-port negative level sensitive reset data retention latch to prevent data contention between (QN) and the second data bit (D2).
 7. The dual-port negative level sensitive reset data retention latch of claim 1 wherein the dual-port latch comprises: a first tri-state inverter, the first tri-state inverter having a data input, two control inputs and a data output wherein the data input is electrically connected (QN), the first control input is electrically connected to (SS), and the second control input is connected to (SSN); a second tri-state inverter, the second tri-state inverter having a data input, two control inputs and a data output wherein the data input is electrically connected to the second data bit (D2), the first control input is electrically connected to (SS), and the second control input is connected to (SSN) and the outputs of the first and second tri-state inverter are electrically connected to each other; a clocked inverter, the clocked inverter having a data input, four control inputs and a data output wherein the data input is electrically connected to the data output of the first and second tri-state inverters, a first control input is electrically connected to (CKT), a second control input is connected to (CLKZ), a third control input is electrically connected to (RET) and a fourth control input (REN) and the output of the clocked inverter is electrically connected to the input (QN) of the first tri-state inverter.
 8. A method of writing data into a dual-port latch of a dual-port negative level sensitive reset data retention latch in retention mode comprising; disconnecting a first power supply (VDD1) from a clocked inverter configured to receive a first data bit (D1), clock signal (CKT), clock signal CLKZ, a reset control signal (REN) and retention mode control signal (RET) wherein (CKT), (CLKZ), (REN), and (RET) determine whether the data output (QN) from the clocked inverter is the binary compliment of data bit (D1) or an indeterminate value; connecting a second power supply (VDD2) to the dual-port latch wherein the dual-port latch is configured to receive the output (QN) of the clocked inverter, a second data bit (D2), the clock signal (CKT), the clock signal (CLKZ), the retain control signal (RET), a reset control signal (REN), a latch control signal (SS) and a latch control signal (SSN) wherein signals (CKT), (CLKZ), (RET), (REN), (SS) and (SSN) determine whether the output (QN) of the clocked inverter or the second data bit (D2) is latched in the dual-port latch; entering retention mode by driving the retain control signal (RET) to a logical high value; driving the second data bit (D2) to a binary logical level; writing the second data bit (D2) into the dual-port latch by driving the control signal (SS) to a logical high value and driving the control signal (SSN) to a logical low value; latching the second data bit (D2) into the dual-port latch by driving the control signal (SS) to a logical low value and driving the control signal (SSN) to a logical high value; connecting the first power supply (VDD1) to clocked inverter; exiting the retention mode and entering a functional mode by driving control signal (RET) to a logical low.
 9. A method of writing data to a dual-port latch of a dual-port negative level sensitive reset data retention latch while in a functional mode comprising; entering the functional mode by driving retain control signal (RET) to a logical low value and reset control signal (REN) to a logical high value; tri-stating an output of a clocked inverter by driving a clock signal (CKT) to a logical high level and by driving a clock signal (CKZ) to a logical low level; driving a second data bit (D2) of the dual port latch to a binary logical level wherein the dual-port latch is configured to receive the output of the clocked inverter, a second data bit (D2), the clock signal (CKT), the binary logical compliment signal (CLKZ) of the clock signal (CKT), the retain control signal (RET), the reset control signal (REN), a control signal (SS) and the binary logical compliment signal (SSN) of the control signal (SS) wherein signals (CKT), (CLKZ), (RET), (PREN), (SS) and (SSN) determine whether the output (QN) of the clocked inverter or the second data bit (D2) is latched in the dual-port latch; writing the second data bit (D2) into the dual-port latch by driving the control signal (SS) to a logical high value and driving the control signal (SSN) to a logical low value; latching the second data bit (D2) into the dual-port latch by driving the control signal (SS) to a logical low value and driving the control signal (SSN) to a logical high value; allowing CKT and CLKZ to toggle. 